1. Field of the Invention
The present invention relates to a method of analyzing electromagnetic interference (EMI) (hereinafter often referred to as an “EMI analysis method”), and more particularly, to a method of analyzing electromagnetic interference arising in a large-scale, high-speed LSI (large-scale integrated circuit) by means of high-speed, highly accurate logic simulation.
2. Description of the Related Art
LSIs are used in a broadening range of applications, from communications devices, such as cellular phones, to general household products, toys, and automobiles, as well as applications in the field of computers. Electromagnetic interference arising in such products induces radio interference noise in a nearby RF receiver, such as a TV set or a radio, or in faulty operation of another nearby system. In order to prevent this problem, the whole product is shielded, or filters are provided in the product In order to reduce the need to increase the complexity and cost of production and to reduce the difficulties encountered in conventional methods of preventing occurrence of electromagnetic interference in a product, strong demand exists for a means of suppression of noise in an LSI itself.
An LSI is a key component of any product in which it is used. Demand exists for a larger-scale, high-speed LSI in order to ensure the competitiveness of a product. As product development cycles become shorter, design-automation of LSIs has become indispensable for satisfying the demand. There is a growing need for adopting synchronous circuitry in LSIs in order to take advantage of state-of-the-art design-automation methods. When all of the circuits of a large-scale, high-speed LSI operate synchronously with a reference dock signal, instantaneously-changing current becomes very large resulting in an increase in the induction of electromagnetic interference.
The present invention relates to a simulation method that enables evaluation of EMI indispensable for reducing electromagnetic interference while maintaining a tendency toward a larger-scale, higher-speed LSI.
Noise imposed on another device by an LSI is roughly classified into two types: radiation noise, and conduction noise. Radiation noise emanated directly from an LSI includes noise emitted from internal wires of an LSI. However, the internal wires are not large enough to act as an effective antenna. As operating frequencies of LSIs continue to increase, it is expected that the radiation noise emitted directly from an LSI will pose a problem in the future. However, as of now, the noise emitted from the inside of an LSI is considered trivial.
In contrast, conduction noise from an LSI affects other devices mounted on the same printed circuit board, by way of direct interconnections, such as external leads of the LSI or traces provided on the printed circuit board. The interconnections act as the source of origination or as an antenna for emitting conduction noise. The antenna constituted of the interconnections is much larger than that constituted by internal wires of an LSI and is a dominant element In terms of electromagnetic emission.
A power line and a signal line can act as paths along which conduction noise developing in an LSI travels. When analyzing an electromagnetic field in the vicinity of an LSI, noise which results from variation in an electric current of a power source being emitted from a power line serving as an antenna is considered to be dominant. In some cases, ringing and overshoot phenomena stemming from variation in a signal may also pose problems. However, variation in an internal power level of an LSI that propagates as a signal waveform more often presents a problem. Noise emitted from a power line or a signal line is considered to have a strong correlation with variation in the electric current of a power source (hereinafter referred to as a “source current”).
A source current of a CMOS circuit will now be described by reference to a simple inverter circuit. When variation arises in a voltage applied to an inverter circuit, a load capacity charge/discharge current flows, which is the primary source current of the CMOS circuit. In addition, a short circuit current flows together with the load capacity charge/discharge current. In automated design of such a CMOS circuit, all circuits of an LSI are synchronized In accordance with the constraints of the design-automation tool. As a result of all circuits being synchronized, all circuits of the LSI operate simultaneously, and a peak current arises in a power source in synchronism with a reference clock signal. Further, in order to increase operating speed, or shorten a cycle, of the LSI, the capacity of a transistor is increased so as to enable a charging/discharging operation to be completed within a shorter period of time. Eventually, the peak current increases. Necessarily, the total source current of an LSI is increased when the integration level of an LSI is increased. Thus, the peak current of the power source is increased, thereby inducing an abrupt change in source current. Such an abrupt change induces an increase in higher harmonic components, thereby resulting in an increase in electromagnetic interference.
Highly precise simulation of change in a source current, the primary cause of electromagnetic interference, is considered to be effective in predicting the electromagnetic interference that will arise in an LSI.
A conventional current simulation method for transistor-level current analysis will be described below.
FIG. 15 is a block diagram showing the flow of processing operations of a conventional transistor-level EMI analysis method. According to this method, based on layout data is provided 01 that describes an LSI that is to be analyzed using a transistor-level current analysis method. Layout parameter extraction (hereinafter referred to simply as an “LPE”) processing O3 is performed on the layout data. Subsequently, several processing steps are performed: circuit simulation O6 of a switch-level netlist; source-of-current modeling O8; a power line LPE step O10; transient analysis simulation O12; and fast Fourier transformation (hereinafter abbreviated FFT) processing O14.
Processing pertaining to each of the foregoing processing steps will now be described with reference to FIG. 15.
First, in step O3 data is input: layout data O1 pertaining to a semiconductor integrated circuit to be subjected to EMI analysis; parameters of elements, such as transistor elements or various parasitic wiring elements (e.g., resistors and capacitors); and an LPE rule O2 for defining a form in which extracted layout parameters are to be output. In accordance with the LPE rule O2, parameters of the respective elements included In the layout data O1 are calculated, whereby a netlist O4 is produced. In step O3, parasitic elements of a power source (and the ground) are not extracted.
In step O6 the netlist O4 prepared in step O3 and a test pattern O5 are input. The test pattern is used for causing the circuit being analyzed to replicate a desired logic operation. A load capacity charge/discharge current and a short circuit current are calculated, which correspond to the operating state of an internal circuit, thereby producing current waveform information O7 about the waveform of an electric current of a transistor. The processing of step O6 is based on the assumption that the potential of a power source (and that of ground) is a variation-free, ideal potential.
In step O8 the current waveform information O7 of a transistor prepared in step O6 is entered. The current waveform information O7 is used to prepare current source element model information O9 suitable for subsequent step O12. In order to reduce the processing load for subsequent step O12, a function circuit block consisting of a plurality of transistors is usually modeled as a single current-source element.
The processing performed in step O10 differs from step O3, only in that parameters of parasitic elements of a power source and of a ground wire (e.g., resistors, decoupling capacitance, and like elements) are extracted, rather than parameters of transistor elements and of various parasitic wiring elements. Hence, repeated explanation is omitted. In step O10, a power source (and ground) wiring netlist O11 is produced.
In step O12 the current source element model information O9 prepared in step O8 is entered, the power source (and ground) wiring netlist O11 prepared in step O10 is entered, and impedance O16 of a wire or a lead frame (including, resistance, capacitance, and inductance) is entered. Through analysis of these input data carried out by a transient analysis simulator typified by SPICE, fluctuations in line voltage of a subject circuit are calculated. Thus, a line voltage drop result O17 is produced which corresponds to these fluctuations in line voltage.
Subsequently, the processing of step O6 is performed again. In contrast with the first operation of the processing of step O6 which was based on the assumption that the potential of the power source (and the ground) is a fluctuation-free, ideal potential, the line voltage drop result O17 prepared in step O12 is entered. The current waveform information O7 for a transistor is prepared again with consideration of fluctuations in line voltage. Similarly, processing of steps O8 and O12 is repeated.
Steps O6, O8, and O12 are repeated several times, thereby producing a current waveform result O13 that very accurately simulates fluctuations in line voltage.
In step O14, the current waveform result O13 prepared in step O12 is entered and subjected to FFT processing, to thereby enable frequency spectrum analysis. Thus, an EMI analysis result O15 is obtained.
In the conventional example, the precision of verification varies greatly according to the combination of the LPE processing O3, the power line LPE processing O10, and the source current modeling processing O8. However, a certain level of accuracy of analysis can be expected. A transient analysis simulator typified by SPICE is limited to transistor-level analysis of an electric current and thus, an enormous amount of processing time is required. Since the integration level of semiconductor integrated circuits has increased recently, establishment of an EMI analysis method is desired to enable high-speed analysis of an electric current on a higher level than a transistor level
A gate-level current analysis method has conventionally been proposed as a current analysis method that can be made faster. This gate-level current analysis method is used for analyzing power consumption. One example of a gate-level current analysis method is EMI-noise analysis that is performed in an ASIC design environment. This method is described in “EMI-Noise Analysis Under ASIC Design Environment” (ISPD&99, pp. 16 through 21). According to this technique, an event is acquired from the result of a gate-level simulation using a test vector, and the waveform of an electric current is estimated. The frequency of the thus-estimated current waveform is analyzed using FFT processing. More specifically, as shown in FIG. 16, a logic simulation 104 is based on a netlist 101 and a test vector 102, wherewith event information 105 is calculated. Based on this event information 105 and on waveform information 103 obtained at the time of toggling, processing for a current waveform calculation section 107 is executed, producing a current waveform calculation result 108. This current waveform calculation result 108 is subjected to FFT processing 109 to produce a frequency characteristic 110. The EMI-noise analysis method can perform an EMI analysis operation faster than the conventional gate-level EMI analysis method. However, use of a test vector still involves consumption of substantial execution time. Therefore, the processing speed achieved by the aforementioned EMI-noise analysis method is not sufficiently high, and demand still exists for faster EMI-noise analysis method. Another problem with the aforementioned EMI-noise analysis method is that the analysis result is dependent on the pattern of the test vector employed.
As mentioned above, the conventional example using the transistor-level current analysis method can be expected to yield a certain level of accuracy. However, a transient analysis simulator typified by SPICE is used for such a transistor-level current analysis. As such, a limitation is imposed on the level of a circuit to be analyzed, and an enormous amount of processing time is required. The level of semiconductor integrated circuits has recently increased, and thus there is a need for an EMI analysis method that enables high-speed analysis of an electric current at a scale larger than that which can be analyzed by a transistor-level simulator.
Gate-level simulation using a test vector has also been proposed. However, the example conventional gate-level simulation technique does not sufficiently increase the speed of analysis. Since the gate-level simulation technique employs a test vector, an analysis result is dependent on the test pattern employed.